LOGIC BEES

LOGIC BEES

 

Description:
Being able to design logics is one of the important qualities in an Engineer. This event is called “Logic Bees”. 

In this event, problems will test participant’s grasp over Digital Logic Design (which includes timers, counters, gates and flip flops etc. So, the pre-requisites of this competition are related courses of Digital Logic Design. 

In Logic Bees, you can bring out the best logic for anything. Your ability to handle 0’s and 1’s, and your control over the ICs will be tested to the limits. In this event, your technical skills will be racing against time. This competition is best suited for DLD craze students. 

 

Rules & Regulations:

In this competition, a question paper will be provided to the participants, and they will have to implement it on the breadboard. The person who implements the circuit correctly in the shortest time is declared winner. This competition will test the skills of circuit optimization, neatness of the circuit.  

  1. Each team will consist of 3 members.
  2. Conversation and sharing of any material between teams is strictly prohibited.
  3. The duration of contest will be 2 hours.
  4. Prerequisites for this competition include concepts related to Digital Logic Design.
  5. Datasheets for the IC's will be provided.
  6. Supplies, components and wires will also be provided to the participants.
  7. Participants have only one chance to get their circuit evaluated. There would be no second chance.
  8. Once a team announces the completion of their circuit, time will be noted and team would have to leave the table.
  9. The decision of the management would be final.
  10. Decision of the adjudicators would be final and the participants cannot appeal against it.
  11. If the participant has any related query, consult the moderator of the contest before the session starts as such queries will not be entertained during the contest.

 

Judgment Rules:

  1. Time in which circuit is implemented.
  2. Working condition of the circuit.
  3. Neatness of the circuit.
  4. Any helping material, if found, or any cheating attempt will lead to disqualification from the competition.
  5. The decision of the management would be final.
  6. Decision of the adjudicators would be final and the participants cannot appeal against it.
  7. If the participant has any related query, consult the moderator of the contest before the session starts as such queries will not be entertained during the contest.

 

Software’s allowed:

No software’s are required in this Competition as in this competition the participants will be provided with the necessary stationary (Charts, Markers, Ball pen, Pencils etc.)

 

Equipment:
74LS00 Quad NAND Gate  

74LS02 Quad NOR Gate 

74LS08 Quad AND Gate  

74LS32 Quad OR Gate  

74LS86 Quad XOR Gate  

74LS04 HEX NOT Gate  

74HC7277 Quad XNOR Gate Seven Segment (common cathode)  

 

Registration:
Rs.500 per team, Maximum 3 members are allowed per team.(For University)

 

Winning Prize:

1st Position: Exclusive Prize

2nd Position: Exclusive Prize 


Register Now

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